Cascoda SDK
Cascoda SDK for building software to run with CA-821x transceivers
partition_M2351.h
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1 /**************************************************************************/
11 #ifndef PARTITION_M2351
12 #define PARTITION_M2351
13 
14 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
15 
16 /*
17  Default M2351 pritition configuration file is for non-TrustZone sample code only.
18  If user wants to use TrurstZone, they should have their partition_m2351.h.
19  For TrustZone projects, path of local partition_m2351.h should be in the
20  front of the include path list to make sure local partition_m2351.h is used.
21 
22  It also apply to non-secure project of the TrustZone projects.
23 
24 */
25 #error "Link to default partition_m2351.h in secure mode. Please check your include path."
26 
27 #endif
28 
29 /*
30 //-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
31 */
32 
33 /*
34  SRAMNSSET
35 */
36 /*
37 // Bit 0..16
38 // <o.0..16> Secure SRAM Size <0=> 0 KB
39 // <0x2000=> 8KB
40 // <0x4000=> 16KB
41 // <0x6000=> 24KB
42 // <0x8000=> 32KB
43 // <0xa000=> 40KB
44 // <0xc000=> 48KB
45 // <0xe000=> 56KB
46 // <0x10000=> 64KB
47 // <0x12000=> 72KB
48 // <0x14000=> 80KB
49 // <0x16000=> 88KB
50 // <0x18000=> 96KB
51 */
52 #define SCU_SECURE_SRAM_SIZE 0x18000
53 #define NON_SECURE_SRAM_BASE (0x30000000 + SCU_SECURE_SRAM_SIZE)
54 
55 /*--------------------------------------------------------------------------------------------------------*/
56 
57 /*
58  NSBA
59 */
60 #define FMC_INIT_NSBA 1
61 /*
62 // <o>Secure Flash ROM Size <0x800-0x80000:0x800>
63 */
64 
65 #define FMC_SECURE_ROM_SIZE 0x80000
66 
67 #define FMC_NON_SECURE_BASE (0x10000000 + FMC_SECURE_ROM_SIZE)
68 
69 /*--------------------------------------------------------------------------------------------------------*/
70 
71 /*
72 // <h> Peripheral Secure Attribution Configuration
73 */
74 
75 /*
76  PNSSET0
77 */
78 /*
79 // Module 0..31
80 // <o.9> USBH <0=> Secure <1=> Non-Secure
81 // <o.13> SD0 <0=> Secure <1=> Non-Secure
82 // <o.16> EBI <0=> Secure <1=> Non-Secure
83 // <o.24> PDMA1 <0=> Secure <1=> Non-Secure
84 */
85 #define SCU_INIT_PNSSET0_VAL 0x0
86 /*
87  PNSSET1
88 */
89 /*
90 // Module 0..31
91 // <o.17> CRC <0=> Secure <1=> Non-Secure
92 // <o.18> CRPT <0=> Secure <1=> Non-Secure
93 */
94 #define SCU_INIT_PNSSET1_VAL 0x00000
95 /*
96  PNSSET2
97 */
98 /*
99 // Module 0..31
100 // <o.1> RTC <0=> Secure <1=> Non-Secure
101 // <o.3> EADC <0=> Secure <1=> Non-Secure
102 // <o.5> ACMP01 <0=> Secure <1=> Non-Secure
103 //
104 // <o.7> DAC <0=> Secure <1=> Non-Secure
105 // <o.8> I2S0 <0=> Secure <1=> Non-Secure
106 // <o.13> OTG <0=> Secure <1=> Non-Secure
107 // <o.17> TMR23 <0=> Secure <1=> Non-Secure
108 // <h> EPWM
109 // <o.24> EPWM0 <0=> Secure <1=> Non-Secure
110 // <o.25> EPWM1 <0=> Secure <1=> Non-Secure
111 // <o.26> BPWM0 <0=> Secure <1=> Non-Secure
112 // <o.27> BPWM1 <0=> Secure <1=> Non-Secure
113 // </h>
114 */
115 #define SCU_INIT_PNSSET2_VAL 0x0
116 /*
117  PNSSET3
118 */
119 /*
120 // Module 0..31
121 // <h> SPI
122 // <o.0> QSPI0 <0=> Secure <1=> Non-Secure
123 // <o.1> SPI0 <0=> Secure <1=> Non-Secure
124 // <o.2> SPI1 <0=> Secure <1=> Non-Secure
125 // <o.3> SPI2 <0=> Secure <1=> Non-Secure
126 // <o.4> SPI3 <0=> Secure <1=> Non-Secure
127 // </h>
128 // <h> UART
129 // <o.16> UART0 <0=> Secure <1=> Non-Secure
130 // <o.17> UART1 <0=> Secure <1=> Non-Secure
131 // <o.18> UART2 <0=> Secure <1=> Non-Secure
132 // <o.19> UART3 <0=> Secure <1=> Non-Secure
133 // <o.20> UART4 <0=> Secure <1=> Non-Secure
134 // <o.21> UART5 <0=> Secure <1=> Non-Secure
135 // </h>
136 */
137 #define SCU_INIT_PNSSET3_VAL 0x00000
138 /*
139  PNSSET4
140 */
141 /*
142 // Module 0..31
143 // <h> I2C
144 // <o.0> I2C0 <0=> Secure <1=> Non-Secure
145 // <o.1> I2C1 <0=> Secure <1=> Non-Secure
146 // <o.2> I2C2 <0=> Secure <1=> Non-Secure
147 // </h>
148 // <h> Smart Card
149 // <o.16> SC0 <0=> Secure <1=> Non-Secure
150 // <o.17> SC1 <0=> Secure <1=> Non-Secure
151 // <o.18> SC2 <0=> Secure <1=> Non-Secure
152 // </h>
153 */
154 #define SCU_INIT_PNSSET4_VAL 0x0
155 /*
156  PNSSET5
157 */
158 /*
159 // Module 0..31
160 // <o.0> CAN0 <0=> Secure <1=> Non-Secure
161 // <h> QEI
162 // <o.16> QEI0 <0=> Secure <1=> Non-Secure
163 // <o.17> QEI1 <0=> Secure <1=> Non-Secure
164 // </h>
165 // <h> ECAP
166 // <o.20> ECAP0 <0=> Secure <1=> Non-Secure
167 // <o.21> ECAP1 <0=> Secure <1=> Non-Secure
168 // </h>
169 // <o.25> TRNG <0=> Secure <1=> Non-Secure
170 */
171 #define SCU_INIT_PNSSET5_VAL 0x0
172 /*
173  PNSSET6
174 */
175 /*
176 // Module 0..31
177 // <o.0> USBD <0=> Secure <1=> Non-Secure
178 // <h> USCI
179 // <o.16> USCI0 <0=> Secure <1=> Non-Secure
180 // <o.17> USCI1 <0=> Secure <1=> Non-Secure
181 // </h>
182 */
183 #define SCU_INIT_PNSSET6_VAL 0x0
184 /*
185 // </h>
186 */
187 
188 /*
189 // <h> GPIO Secure Attribution Configuration
190 */
191 
192 /*
193  IONSSET
194 */
195 /*
196 // Bit 0..31
197 // <o.0> PA <0=> Secure <1=> Non-Secure
198 // <o.1> PB <0=> Secure <1=> Non-Secure
199 // <o.2> PC <0=> Secure <1=> Non-Secure
200 // <o.3> PD <0=> Secure <1=> Non-Secure
201 // <o.4> PE <0=> Secure <1=> Non-Secure
202 // <o.5> PF <0=> Secure <1=> Non-Secure
203 // <o.6> PG <0=> Secure <1=> Non-Secure
204 // <o.7> PH <0=> Secure <1=> Non-Secure
205 */
206 #define SCU_INIT_IONSSET_VAL 0x0
207 /*
208 // </h>
209 */
210 
211 /* ---------------------------------------------------------------------------------------------------- */
212 
213 /*
214 // <e>Secure Attribute Unit (SAU) Control
215 */
216 #define SAU_INIT_CTRL 0
217 
218 /*
219 // <q> Enable SAU
220 // <i> To enable Secure Attribute Unit (SAU).
221 */
222 #define SAU_INIT_CTRL_ENABLE 1
223 
224 /*
225 // <o> All Memory Attribute When SAU is disabled
226 // <0=> All Memory is Secure
227 // <1=> All Memory is Non-Secure
228 // <i> To set the ALLNS bit in SAU CTRL.
229 // <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
230 */
231 #define SAU_INIT_CTRL_ALLNS 0
232 
233 /*
234 // </e>
235 */
236 
237 /*
238 // <h>Enable and Set Secure/Non-Secure region
239 */
240 #define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
241 
242 /*
243 // <e>SAU Region 0
244 // <i> Setup SAU Region 0
245 */
246 #define SAU_INIT_REGION0 0
247 /*
248 // <o>Start Address <0-0xFFFFFFE0>
249 */
250 #define SAU_INIT_START0 0x0003F000 /* start address of SAU region 0 */
251 /*
252 // <o>End Address <0x1F-0xFFFFFFFF>
253 */
254 #define SAU_INIT_END0 0x0003FFFF /* end address of SAU region 0 */
255 /*
256 // <o>Region is
257 // <0=>Non-Secure
258 // <1=>Secure, Non-Secure Callable
259 */
260 #define SAU_INIT_NSC0 1
261 /*
262 // </e>
263 */
264 
265 /*
266 // <e>SAU Region 1
267 // <i> Setup SAU Region 1
268 */
269 #define SAU_INIT_REGION1 0
270 /*
271 // <o>Start Address <0-0xFFFFFFE0>
272 */
273 #define SAU_INIT_START1 0x10040000
274 /*
275 // <o>End Address <0x1F-0xFFFFFFFF>
276 */
277 #define SAU_INIT_END1 0x1007FFFF
278 /*
279 // <o>Region is
280 // <0=>Non-Secure
281 // <1=>Secure, Non-Secure Callable
282 */
283 #define SAU_INIT_NSC1 0
284 /*
285 // </e>
286 */
287 
288 /*
289 // <e>SAU Region 2
290 // <i> Setup SAU Region 2
291 */
292 #define SAU_INIT_REGION2 0
293 /*
294 // <o>Start Address <0-0xFFFFFFE0>
295 */
296 #define SAU_INIT_START2 0x2000F000
297 /*
298 // <o>End Address <0x1F-0xFFFFFFFF>
299 */
300 #define SAU_INIT_END2 0x2000FFFF
301 /*
302 // <o>Region is
303 // <0=>Non-Secure
304 // <1=>Secure, Non-Secure Callable
305 */
306 #define SAU_INIT_NSC2 1
307 /*
308 // </e>
309 */
310 
311 /*
312 // <e>SAU Region 3
313 // <i> Setup SAU Region 3
314 */
315 #define SAU_INIT_REGION3 0
316 /*
317 // <o>Start Address <0-0xFFFFFFE0>
318 */
319 #define SAU_INIT_START3 0x3f000
320 /*
321 // <o>End Address <0x1F-0xFFFFFFFF>
322 */
323 #define SAU_INIT_END3 0x3f7ff
324 /*
325 // <o>Region is
326 // <0=>Non-Secure
327 // <1=>Secure, Non-Secure Callable
328 */
329 #define SAU_INIT_NSC3 1
330 /*
331 // </e>
332 */
333 
334 /*
335  <e>SAU Region 4
336  <i> Setup SAU Region 4
337 */
338 #define SAU_INIT_REGION4 1
339 /*
340  <o>Start Address <0-0xFFFFFFE0>
341 */
342 #define SAU_INIT_START4 FMC_NON_SECURE_BASE /* start address of SAU region 4 */
343 
344 /*
345  <o>End Address <0x1F-0xFFFFFFFF>
346 */
347 #define SAU_INIT_END4 0x1007FFFF /* end address of SAU region 4 */
348 
349 /*
350  <o>Region is
351  <0=>Non-Secure
352  <1=>Secure, Non-Secure Callable
353 */
354 #define SAU_INIT_NSC4 0
355 /*
356  </e>
357 */
358 
359 /*
360  <e>SAU Region 5
361  <i> Setup SAU Region 5
362 */
363 #define SAU_INIT_REGION5 1
364 
365 /*
366  <o>Start Address <0-0xFFFFFFE0>
367 */
368 #define SAU_INIT_START5 0x00807E00
369 
370 /*
371  <o>End Address <0x1F-0xFFFFFFFF>
372 */
373 #define SAU_INIT_END5 0x00807FFF
374 
375 /*
376  <o>Region is
377  <0=>Non-Secure
378  <1=>Secure, Non-Secure Callable
379 */
380 #define SAU_INIT_NSC5 1
381 /*
382  </e>
383 */
384 
385 /*
386  <e>SAU Region 6
387  <i> Setup SAU Region 6
388 */
389 #define SAU_INIT_REGION6 1
390 
391 /*
392  <o>Start Address <0-0xFFFFFFE0>
393 */
394 #define SAU_INIT_START6 NON_SECURE_SRAM_BASE
395 
396 /*
397  <o>End Address <0x1F-0xFFFFFFFF>
398 */
399 #define SAU_INIT_END6 0x30017FFF
400 
401 /*
402  <o>Region is
403  <0=>Non-Secure
404  <1=>Secure, Non-Secure Callable
405 */
406 #define SAU_INIT_NSC6 0
407 /*
408  </e>
409 */
410 
411 /*
412  <e>SAU Region 7
413  <i> Setup SAU Region 7
414 */
415 #define SAU_INIT_REGION7 1
416 
417 /*
418  <o>Start Address <0-0xFFFFFFE0>
419 */
420 #define SAU_INIT_START7 0x50000000
421 
422 /*
423  <o>End Address <0x1F-0xFFFFFFFF>
424 */
425 #define SAU_INIT_END7 0x5FFFFFFF
426 
427 /*
428  <o>Region is
429  <0=>Non-Secure
430  <1=>Secure, Non-Secure Callable
431 */
432 #define SAU_INIT_NSC7 0
433 /*
434  </e>
435 */
436 
437 /*
438 // </h>
439 */
440 
441 /*
442 // <e>Setup behavior of Sleep and Exception Handling
443 */
444 #define SCB_CSR_AIRCR_INIT 1
445 
446 /*
447 // <o> Deep Sleep can be enabled by
448 // <0=>Secure and Non-Secure state
449 // <1=>Secure state only
450 // <i> Value for SCB->CSR register bit DEEPSLEEPS
451 */
452 #define SCB_CSR_DEEPSLEEPS_VAL 0
453 
454 /*
455 // <o>System reset request accessible from
456 // <0=> Secure and Non-Secure state
457 // <1=> Secure state only
458 // <i> Value for SCB->AIRCR register bit SYSRESETREQS
459 */
460 #define SCB_AIRCR_SYSRESETREQS_VAL 0
461 
462 /*
463 // <o>Priority of Non-Secure exceptions is
464 // <0=> Not altered
465 // <1=> Lowered to 0x80-0xFF
466 // <i> Value for SCB->AIRCR register bit PRIS
467 */
468 #define SCB_AIRCR_PRIS_VAL 0
469 
470 /* Assign HardFault to be always secure for safe */
471 #define SCB_AIRCR_BFHFNMINS_VAL 0
472 
473 /*
474 // </e>
475 */
476 
477 /*
478  max 128 SAU regions.
479  SAU regions are defined in partition.h
480  */
481 
482 #define SAU_INIT_REGION(n) \
483  SAU->RNR = (n & SAU_RNR_REGION_Msk); \
484  SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
485  SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
486 
487 #endif /* PARTITION_M2351 */