Cascoda SDK
Cascoda SDK for building software to run with CA-821x transceivers
partition_M2351.h
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1 /**************************************************************************/
13 #ifndef PARTITION_M2351
14 #define PARTITION_M2351
15 #define CUSTOM_PARTITION_H
16 
17 /*
18 //-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
19 */
20 
21 /*
22  SRAMNSSET
23 */
24 /*
25 // Bit 0..16
26 // <o.0..16> Secure SRAM Size <0=> 0 KB
27 // <0x2000=> 8KB
28 // <0x4000=> 16KB
29 // <0x6000=> 24KB
30 // <0x8000=> 32KB
31 // <0xa000=> 40KB
32 // <0xc000=> 48KB
33 // <0xe000=> 56KB
34 // <0x10000=> 64KB
35 // <0x12000=> 72KB
36 // <0x14000=> 80KB
37 // <0x16000=> 88KB
38 // <0x18000=> 96KB
39 */
40 #define SCU_SECURE_SRAM_SIZE 0x4000
41 #define NON_SECURE_SRAM_BASE (0x30000000 + SCU_SECURE_SRAM_SIZE)
42 
43 /*--------------------------------------------------------------------------------------------------------*/
44 
45 /*
46  NSBA
47 */
48 #define FMC_INIT_NSBA 1
49 /*
50 // <o>Secure Flash ROM Size <0x800-0x7FFFF:0x800>
51 */
52 
53 #define FMC_SECURE_ROM_SIZE 0x10000
54 
55 #define FMC_NON_SECURE_BASE (0x10000000 + FMC_SECURE_ROM_SIZE)
56 
57 /*--------------------------------------------------------------------------------------------------------*/
58 
59 /*
60 // <h> Peripheral Secure Attribution Configuration
61 */
62 
63 /*
64  PNSSET0
65 */
66 /*
67 // Module 0..31
68 // <o.9> USBH <0=> Secure <1=> Non-Secure
69 // <o.13> SD0 <0=> Secure <1=> Non-Secure
70 // <o.16> EBI <0=> Secure <1=> Non-Secure
71 // <o.24> PDMA1 <0=> Secure <1=> Non-Secure
72 */
73 #define SCU_INIT_PNSSET0_VAL 0x1012200
74 /*
75  PNSSET1
76 */
77 /*
78 // Module 0..31
79 // <o.17> CRC <0=> Secure <1=> Non-Secure
80 // <o.18> CRPT <0=> Secure <1=> Non-Secure
81 */
82 #define SCU_INIT_PNSSET1_VAL 0x60000
83 /*
84  PNSSET2
85 */
86 /*
87 // Module 0..31
88 // <o.1> RTC <0=> Secure <1=> Non-Secure
89 // <o.3> EADC <0=> Secure <1=> Non-Secure
90 // <o.5> ACMP01 <0=> Secure <1=> Non-Secure
91 //
92 // <o.7> DAC <0=> Secure <1=> Non-Secure
93 // <o.8> I2S0 <0=> Secure <1=> Non-Secure
94 // <o.13> OTG <0=> Secure <1=> Non-Secure
95 // <o.17> TMR23 <0=> Secure <1=> Non-Secure
96 // <h> EPWM
97 // <o.24> EPWM0 <0=> Secure <1=> Non-Secure
98 // <o.25> EPWM1 <0=> Secure <1=> Non-Secure
99 // <o.26> BPWM0 <0=> Secure <1=> Non-Secure
100 // <o.27> BPWM1 <0=> Secure <1=> Non-Secure
101 // </h>
102 */
103 #define SCU_INIT_PNSSET2_VAL 0xf0221a8
104 /*
105  PNSSET3
106 */
107 /*
108 // Module 0..31
109 // <h> SPI
110 // <o.0> SPI0 <0=> Secure <1=> Non-Secure
111 // <o.1> SPI1 <0=> Secure <1=> Non-Secure
112 // <o.2> SPI2 <0=> Secure <1=> Non-Secure
113 // <o.3> SPI3 <0=> Secure <1=> Non-Secure
114 // <o.4> SPI4 <0=> Secure <1=> Non-Secure
115 // <o.5> SPI5 <0=> Secure <1=> Non-Secure
116 // </h>
117 // <h> UART
118 // <o.16> UART0 <0=> Secure <1=> Non-Secure
119 // <o.17> UART1 <0=> Secure <1=> Non-Secure
120 // <o.18> UART2 <0=> Secure <1=> Non-Secure
121 // <o.19> UART3 <0=> Secure <1=> Non-Secure
122 // <o.20> UART4 <0=> Secure <1=> Non-Secure
123 // <o.21> UART5 <0=> Secure <1=> Non-Secure
124 // </h>
125 */
126 #define SCU_INIT_PNSSET3_VAL 0x3f001f
127 /*
128  PNSSET4
129 */
130 /*
131 // Module 0..31
132 // <h> I2C
133 // <o.0> I2C0 <0=> Secure <1=> Non-Secure
134 // <o.1> I2C1 <0=> Secure <1=> Non-Secure
135 // <o.2> I2C2 <0=> Secure <1=> Non-Secure
136 // </h>
137 // <h> Smart Card
138 // <o.16> SC0 <0=> Secure <1=> Non-Secure
139 // <o.17> SC1 <0=> Secure <1=> Non-Secure
140 // <o.18> SC2 <0=> Secure <1=> Non-Secure
141 // </h>
142 */
143 #define SCU_INIT_PNSSET4_VAL 0x70007
144 /*
145  PNSSET5
146 */
147 /*
148 // Module 0..31
149 // <o.0> CAN0 <0=> Secure <1=> Non-Secure
150 // <h> QEI
151 // <o.16> QEI0 <0=> Secure <1=> Non-Secure
152 // <o.17> QEI1 <0=> Secure <1=> Non-Secure
153 // </h>
154 // <h> ECAP
155 // <o.20> ECAP0 <0=> Secure <1=> Non-Secure
156 // <o.21> ECAP1 <0=> Secure <1=> Non-Secure
157 // </h>
158 // <o.23> DSRC <0=> Secure <1=> Non-Secure
159 //
160 // <o.25> TRNG <0=> Secure <1=> Non-Secure
161 */
162 #define SCU_INIT_PNSSET5_VAL 0x2330001
163 /*
164  PNSSET6
165 */
166 /*
167 // Module 0..31
168 // <o.0> USBD <0=> Secure <1=> Non-Secure
169 // <h> USCI
170 // <o.16> USCI0 <0=> Secure <1=> Non-Secure
171 // <o.17> USCI1 <0=> Secure <1=> Non-Secure
172 // </h>
173 */
174 #define SCU_INIT_PNSSET6_VAL 0x30001
175 /*
176 // </h>
177 */
178 
179 /*
180 // <h> GPIO Secure Attribution Configuration
181 */
182 
183 /*
184  IONSSET
185 */
186 /*
187 // Bit 0..31
188 // <o.0> PA <0=> Secure <1=> Non-Secure
189 // <o.1> PB <0=> Secure <1=> Non-Secure
190 // <o.2> PC <0=> Secure <1=> Non-Secure
191 // <o.3> PD <0=> Secure <1=> Non-Secure
192 // <o.4> PE <0=> Secure <1=> Non-Secure
193 // <o.5> PF <0=> Secure <1=> Non-Secure
194 // <o.6> PG <0=> Secure <1=> Non-Secure
195 // <o.7> PH <0=> Secure <1=> Non-Secure
196 */
197 #define SCU_INIT_IONSSET_VAL 0xff
198 /*
199 // </h>
200 */
201 
202 /* ---------------------------------------------------------------------------------------------------- */
203 
204 /*
205 // <e>Secure Attribute Unit (SAU) Control
206 */
207 #define SAU_INIT_CTRL 1
208 
209 /*
210 // <q> Enable SAU
211 // <i> To enable Secure Attribute Unit (SAU).
212 */
213 #define SAU_INIT_CTRL_ENABLE 1
214 
215 /*
216 // <o> All Memory Attribute When SAU is disabled
217 // <0=> All Memory is Secure
218 // <1=> All Memory is Non-Secure
219 // <i> To set the ALLNS bit in SAU CTRL.
220 // <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
221 */
222 #define SAU_INIT_CTRL_ALLNS 0
223 
224 /*
225 // </e>
226 */
227 
228 /*
229 // <h>Enable and Set Secure/Non-Secure region
230 */
231 #define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
232 
233 /*
234 // <e>SAU Region 0
235 // <i> Setup SAU Region 0
236  * Non secure callable veneer
237 */
238 #define SAU_INIT_REGION0 1
239 /*
240 // <o>Start Address <0-0xFFFFFFE0>
241 */
242 #define SAU_INIT_START0 0xf800 /* start address of SAU region 0 */
243 /*
244 // <o>End Address <0x1F-0xFFFFFFFF>
245 */
246 #define SAU_INIT_END0 0xffff /* end address of SAU region 0 */
247 /*
248 // <o>Region is
249 // <0=>Non-Secure
250 // <1=>Secure, Non-Secure Callable
251 */
252 #define SAU_INIT_NSC0 1
253 /*
254 // </e>
255 */
256 
257 /*
258 // <e>SAU Region 1
259 // <i> Setup SAU Region 1
260 */
261 #define SAU_INIT_REGION1 0
262 /*
263 // <o>Start Address <0-0xFFFFFFE0>
264 */
265 #define SAU_INIT_START1 0x10010000
266 /*
267 // <o>End Address <0x1F-0xFFFFFFFF>
268 */
269 #define SAU_INIT_END1 0x1007FFFF
270 /*
271 // <o>Region is
272 // <0=>Non-Secure
273 // <1=>Secure, Non-Secure Callable
274 */
275 #define SAU_INIT_NSC1 0
276 /*
277 // </e>
278 */
279 
280 /*
281 // <e>SAU Region 2
282 // <i> Setup SAU Region 2
283  * Secure flash (disabled - secure by default)
284 */
285 #define SAU_INIT_REGION2 0
286 /*
287 // <o>Start Address <0-0xFFFFFFE0>
288 */
289 #define SAU_INIT_START2 0x2000F000
290 /*
291 // <o>End Address <0x1F-0xFFFFFFFF>
292 */
293 #define SAU_INIT_END2 0x2000FFFF
294 /*
295 // <o>Region is
296 // <0=>Non-Secure
297 // <1=>Secure, Non-Secure Callable
298 */
299 #define SAU_INIT_NSC2 1
300 /*
301 // </e>
302 */
303 
304 /*
305 // <e>SAU Region 3
306 // <i> Setup SAU Region 3
307  * not used
308 */
309 #define SAU_INIT_REGION3 0
310 /*
311 // <o>Start Address <0-0xFFFFFFE0>
312 */
313 #define SAU_INIT_START3 0xf800
314 /*
315 // <o>End Address <0x1F-0xFFFFFFFF>
316 */
317 #define SAU_INIT_END3 0xffff
318 /*
319 // <o>Region is
320 // <0=>Non-Secure
321 // <1=>Secure, Non-Secure Callable
322 */
323 #define SAU_INIT_NSC3 1
324 /*
325 // </e>
326 */
327 
328 /*
329  <e>SAU Region 4
330  <i> Setup SAU Region 4
331  Nonsecure flash
332 */
333 #define SAU_INIT_REGION4 1
334 /*
335  <o>Start Address <0-0xFFFFFFE0>
336 */
337 #define SAU_INIT_START4 FMC_NON_SECURE_BASE /* start address of SAU region 4 */
338 
339 /*
340  <o>End Address <0x1F-0xFFFFFFFF>
341 */
342 #define SAU_INIT_END4 0x1007FFFF /* end address of SAU region 4 */
343 
344 /*
345  <o>Region is
346  <0=>Non-Secure
347  <1=>Secure, Non-Secure Callable
348 */
349 #define SAU_INIT_NSC4 0
350 /*
351  </e>
352 */
353 
354 /*
355  <e>SAU Region 5
356  <i> Setup SAU Region 5
357 */
358 #define SAU_INIT_REGION5 0
359 
360 /*
361  <o>Start Address <0-0xFFFFFFE0>
362 */
363 #define SAU_INIT_START5 0x00807E00
364 
365 /*
366  <o>End Address <0x1F-0xFFFFFFFF>
367 */
368 #define SAU_INIT_END5 0x00807FFF
369 
370 /*
371  <o>Region is
372  <0=>Non-Secure
373  <1=>Secure, Non-Secure Callable
374 */
375 #define SAU_INIT_NSC5 1
376 /*
377  </e>
378 */
379 
380 /*
381  <e>SAU Region 6
382  <i> Setup SAU Region 6
383  Nonsecure sram
384 */
385 #define SAU_INIT_REGION6 1
386 
387 /*
388  <o>Start Address <0-0xFFFFFFE0>
389 */
390 #define SAU_INIT_START6 NON_SECURE_SRAM_BASE
391 
392 /*
393  <o>End Address <0x1F-0xFFFFFFFF>
394 */
395 #define SAU_INIT_END6 0x30017FFF
396 
397 /*
398  <o>Region is
399  <0=>Non-Secure
400  <1=>Secure, Non-Secure Callable
401 */
402 #define SAU_INIT_NSC6 0
403 /*
404  </e>
405 */
406 
407 /*
408  <e>SAU Region 7
409  <i> Setup SAU Region 7
410 */
411 #define SAU_INIT_REGION7 1
412 
413 /*
414  <o>Start Address <0-0xFFFFFFE0>
415 */
416 #define SAU_INIT_START7 0x50000000
417 
418 /*
419  <o>End Address <0x1F-0xFFFFFFFF>
420 */
421 #define SAU_INIT_END7 0x5FFFFFFF
422 
423 /*
424  <o>Region is
425  <0=>Non-Secure
426  <1=>Secure, Non-Secure Callable
427 */
428 #define SAU_INIT_NSC7 0
429 /*
430  </e>
431 */
432 
433 /*
434 // </h>
435 */
436 
437 /*
438 // <e>Setup behavior of Sleep and Exception Handling
439 */
440 #define SCB_CSR_AIRCR_INIT 1
441 
442 /*
443 // <o> Deep Sleep can be enabled by
444 // <0=>Secure and Non-Secure state
445 // <1=>Secure state only
446 // <i> Value for SCB->CSR register bit DEEPSLEEPS
447 */
448 #define SCB_CSR_DEEPSLEEPS_VAL 0
449 
450 /*
451 // <o>System reset request accessible from
452 // <0=> Secure and Non-Secure state
453 // <1=> Secure state only
454 // <i> Value for SCB->AIRCR register bit SYSRESETREQS
455 */
456 #define SCB_AIRCR_SYSRESETREQS_VAL 0
457 
458 /*
459 // <o>Priority of Non-Secure exceptions is
460 // <0=> Not altered
461 // <1=> Lowered to 0x80-0xFF
462 // <i> Value for SCB->AIRCR register bit PRIS
463 */
464 #define SCB_AIRCR_PRIS_VAL 0
465 
466 /* Assign HardFault to be always secure for safe */
467 #define SCB_AIRCR_BFHFNMINS_VAL 0
468 
469 /*
470 // </e>
471 */
472 
473 /*
474 // <h>Assign Interrupt to Secure or Non-secure Vector
475 */
476 
477 /*
478  Initialize ITNS 0 (Interrupts 0..31)
479 */
480 #define NVIC_INIT_ITNS0 1
481 /*
482 // BODOUT Always secure
483 // IRC Always secure
484 // PWRWU_ Always secure
485 // SRAM_PERR Always secure
486 // CLKFAIL Always secure
487 
488 // <o.6> RTC <0=> Secure <1=> Non-Secure
489 // <o.7> TAMPER <0=> Secure <1=> Non-Secure
490 // WDT Always secure
491 // WWDT Always secure
492 // <h> EINT
493 // <o.10> EINT0 <0=> Secure <1=> Non-Secure
494 // <o.11> EINT1 <0=> Secure <1=> Non-Secure
495 // <o.12> EINT2 <0=> Secure <1=> Non-Secure
496 // <o.13> EINT3 <0=> Secure <1=> Non-Secure
497 // <o.14> EINT4 <0=> Secure <1=> Non-Secure
498 // <o.15> EINT5 <0=> Secure <1=> Non-Secure
499 // </h>
500 // <h> GPIO
501 // <o.16> GPA <0=> Secure <1=> Non-Secure
502 // <o.17> GPB <0=> Secure <1=> Non-Secure
503 // <o.18> GPC <0=> Secure <1=> Non-Secure
504 // <o.19> GPD <0=> Secure <1=> Non-Secure
505 // <o.20> GPE <0=> Secure <1=> Non-Secure
506 // <o.21> GPF <0=> Secure <1=> Non-Secure
507 // </h>
508 // <o.22> SPI0 <0=> Secure <1=> Non-Secure
509 // <o.23> SPI1 <0=> Secure <1=> Non-Secure
510 // <h> EPWM
511 // <o.24> BRAKE0 <0=> Secure <1=> Non-Secure
512 // <o.25> EPWM0_P0 <0=> Secure <1=> Non-Secure
513 // <o.26> EPWM0_P1 <0=> Secure <1=> Non-Secure
514 // <o.27> EPWM0_P2 <0=> Secure <1=> Non-Secure
515 // <o.28> BRAKE1 <0=> Secure <1=> Non-Secure
516 // <o.29> EPWM1_P0 <0=> Secure <1=> Non-Secure
517 // <o.30> EPWM1_P1 <0=> Secure <1=> Non-Secure
518 // <o.31> EPWM1_P2 <0=> Secure <1=> Non-Secure
519 // </h>
520 //
521 */
522 #define NVIC_INIT_ITNS0_VAL 0x11ff0000
523 
524 /*
525  Initialize ITNS 1 (Interrupts 32..63)
526 */
527 #define NVIC_INIT_ITNS1 1
528 /*
529 // <h> TIMER
530 // TMR0 Always secure
531 // TMR1 Always secure
532 // <o.2> TMR2 <0=> Secure <1=> Non-Secure
533 // <o.3> TMR3 <0=> Secure <1=> Non-Secure
534 // </h>
535 // <o.4> UART0 <0=> Secure <1=> Non-Secure
536 // <o.5> UART1 <0=> Secure <1=> Non-Secure
537 // <o.6> I2C0 <0=> Secure <1=> Non-Secure
538 // <o.7> I2C1 <0=> Secure <1=> Non-Secure
539 // PDMA0 is secure only
540 // <o.9> DAC <0=> Secure <1=> Non-Secure
541 // <o.10> EADC0 <0=> Secure <1=> Non-Secure
542 // <o.11> EADC1 <0=> Secure <1=> Non-Secure
543 // <o.12> ACMP01 <0=> Secure <1=> Non-Secure
544 
545 // <o.14> EADC2 <0=> Secure <1=> Non-Secure
546 // <o.15> EADC3 <0=> Secure <1=> Non-Secure
547 // <o.16> UART2 <0=> Secure <1=> Non-Secure
548 // <o.17> UART3 <0=> Secure <1=> Non-Secure
549 
550 // <o.19> SPI2 <0=> Secure <1=> Non-Secure
551 // <o.20> SPI3 <0=> Secure <1=> Non-Secure
552 // <o.21> USBD <0=> Secure <1=> Non-Secure
553 // <o.22> USBH <0=> Secure <1=> Non-Secure
554 // <o.23> USBOTG <0=> Secure <1=> Non-Secure
555 // <o.24> CAN0 <0=> Secure <1=> Non-Secure
556 
557 // <h> Smart Card
558 // <o.26> SC0 <0=> Secure <1=> Non-Secure
559 // <o.27> SC1 <0=> Secure <1=> Non-Secure
560 // <o.28> SC2 <0=> Secure <1=> Non-Secure
561 // </h>
562 
563 // <o.30> SPI4 <0=> Secure <1=> Non-Secure
564 
565 //
566 */
567 #define NVIC_INIT_ITNS1_VAL 0x5dfb16fc
568 
569 /*
570  Initialize ITNS 2 (Interrupts 64..95)
571 */
572 #define NVIC_INIT_ITNS2 1
573 /*
574 // <o.0> SDH0 <0=> Secure <1=> Non-Secure
575 
576 
577 
578 // <o.4> I2S0 <0=> Secure <1=> Non-Secure
579 
580 //
581 // <o.7> CRYPTO <0=> Secure <1=> Non-Secure
582 // <o.8> GPG <0=> Secure <1=> Non-Secure
583 
584 // <o.10> UART4 <0=> Secure <1=> Non-Secure
585 // <o.11> UART5 <0=> Secure <1=> Non-Secure
586 // <o.12> USCI0 <0=> Secure <1=> Non-Secure
587 // <o.13> USCI1 <0=> Secure <1=> Non-Secure
588 // <o.14> BPWM0 <0=> Secure <1=> Non-Secure
589 // <o.15> BPWM1 <0=> Secure <1=> Non-Secure
590 
591 
592 // <o.18> I2C2 <0=> Secure <1=> Non-Secure
593 
594 // <o.20> QEI0 <0=> Secure <1=> Non-Secure
595 // <o.21> QEI1 <0=> Secure <1=> Non-Secure
596 // <o.22> ECAP0 <0=> Secure <1=> Non-Secure
597 // <o.23> ECAP1 <0=> Secure <1=> Non-Secure
598 // <o.24> GPH <0=> Secure <1=> Non-Secure
599 // <o.25> EINT7 <0=> Secure <1=> Non-Secure
600 
601 
602 // <o.28> USBH <0=> Secure <1=> Non-Secure
603 
604 
605 
606 //
607 */
608 #define NVIC_INIT_ITNS2_VAL 0x1f0fd99
609 
610 /*
611  Initialize ITNS 3 (Interrupts 96..101)
612 */
613 #define NVIC_INIT_ITNS3 1
614 /*
615 // <o.0> SPI5 <0=> Secure <1=> Non-Secure
616 // <o.1> DSRC <0=> Secure <1=> Non-Secure
617 // <o.2> PDMA1 <0=> Secure <1=> Non-Secure
618 // SCU Always secure
619 //
620 // <o.5> TRNG <0=> Secure <1=> Non-Secure
621 */
622 #define NVIC_INIT_ITNS3_VAL 0x24
623 
624 /*
625 // </h>
626 */
627 
628 /*
629  max 128 SAU regions.
630  SAU regions are defined in partition.h
631  */
632 
633 #define SAU_INIT_REGION(n) \
634  SAU->RNR = (n & SAU_RNR_REGION_Msk); \
635  SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
636  SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
637 #endif /* PARTITION_M2351 */