Cascoda SDK
Cascoda SDK for building software to run with CA-821x transceivers
Macros
partition_M2351.h File Reference

SAU configuration for secure/nonsecure region settings. More...

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Macros

#define CUSTOM_PARTITION_H
 
#define SCU_SECURE_SRAM_SIZE   0x4000
 
#define NON_SECURE_SRAM_BASE   (0x30000000 + SCU_SECURE_SRAM_SIZE)
 
#define FMC_INIT_NSBA   1
 
#define FMC_SECURE_ROM_SIZE   0x10000
 
#define FMC_NON_SECURE_BASE   (0x10000000 + FMC_SECURE_ROM_SIZE)
 
#define SCU_INIT_PNSSET0_VAL   0x1012200
 
#define SCU_INIT_PNSSET1_VAL   0x60000
 
#define SCU_INIT_PNSSET2_VAL   0xf0221a8
 
#define SCU_INIT_PNSSET3_VAL   0x3f001f
 
#define SCU_INIT_PNSSET4_VAL   0x70007
 
#define SCU_INIT_PNSSET5_VAL   0x2330001
 
#define SCU_INIT_PNSSET6_VAL   0x30001
 
#define SCU_INIT_IONSSET_VAL   0xff
 
#define SAU_INIT_CTRL   1
 
#define SAU_INIT_CTRL_ENABLE   1
 
#define SAU_INIT_CTRL_ALLNS   0
 
#define SAU_REGIONS_MAX   8 /* Max. number of SAU regions */
 
#define SAU_INIT_REGION0   1
 
#define SAU_INIT_START0   0xf800 /* start address of SAU region 0 */
 
#define SAU_INIT_END0   0xffff /* end address of SAU region 0 */
 
#define SAU_INIT_NSC0   1
 
#define SAU_INIT_REGION1   0
 
#define SAU_INIT_START1   0x10010000
 
#define SAU_INIT_END1   0x1007FFFF
 
#define SAU_INIT_NSC1   0
 
#define SAU_INIT_REGION2   0
 
#define SAU_INIT_START2   0x2000F000
 
#define SAU_INIT_END2   0x2000FFFF
 
#define SAU_INIT_NSC2   1
 
#define SAU_INIT_REGION3   0
 
#define SAU_INIT_START3   0xf800
 
#define SAU_INIT_END3   0xffff
 
#define SAU_INIT_NSC3   1
 
#define SAU_INIT_REGION4   1
 
#define SAU_INIT_START4   FMC_NON_SECURE_BASE /* start address of SAU region 4 */
 
#define SAU_INIT_END4   0x1007FFFF /* end address of SAU region 4 */
 
#define SAU_INIT_NSC4   0
 
#define SAU_INIT_REGION5   0
 
#define SAU_INIT_START5   0x00807E00
 
#define SAU_INIT_END5   0x00807FFF
 
#define SAU_INIT_NSC5   1
 
#define SAU_INIT_REGION6   1
 
#define SAU_INIT_START6   NON_SECURE_SRAM_BASE
 
#define SAU_INIT_END6   0x30017FFF
 
#define SAU_INIT_NSC6   0
 
#define SAU_INIT_REGION7   1
 
#define SAU_INIT_START7   0x50000000
 
#define SAU_INIT_END7   0x5FFFFFFF
 
#define SAU_INIT_NSC7   0
 
#define SCB_CSR_AIRCR_INIT   1
 
#define SCB_CSR_DEEPSLEEPS_VAL   0
 
#define SCB_AIRCR_SYSRESETREQS_VAL   0
 
#define SCB_AIRCR_PRIS_VAL   0
 
#define SCB_AIRCR_BFHFNMINS_VAL   0
 
#define NVIC_INIT_ITNS0   1
 
#define NVIC_INIT_ITNS0_VAL   0x11ff0000
 
#define NVIC_INIT_ITNS1   1
 
#define NVIC_INIT_ITNS1_VAL   0x5dfb16fc
 
#define NVIC_INIT_ITNS2   1
 
#define NVIC_INIT_ITNS2_VAL   0x1f0fd99
 
#define NVIC_INIT_ITNS3   1
 
#define NVIC_INIT_ITNS3_VAL   0x24
 
#define SAU_INIT_REGION(n)
 

Detailed Description

SAU configuration for secure/nonsecure region settings.

Version
V3.00
Revision
2
Date
16/12/28 1:08p
Note
Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.

Macro Definition Documentation

◆ CUSTOM_PARTITION_H

#define CUSTOM_PARTITION_H

◆ FMC_INIT_NSBA

#define FMC_INIT_NSBA   1

◆ FMC_NON_SECURE_BASE

#define FMC_NON_SECURE_BASE   (0x10000000 + FMC_SECURE_ROM_SIZE)

◆ FMC_SECURE_ROM_SIZE

#define FMC_SECURE_ROM_SIZE   0x10000

◆ NON_SECURE_SRAM_BASE

#define NON_SECURE_SRAM_BASE   (0x30000000 + SCU_SECURE_SRAM_SIZE)

◆ NVIC_INIT_ITNS0

#define NVIC_INIT_ITNS0   1

◆ NVIC_INIT_ITNS0_VAL

#define NVIC_INIT_ITNS0_VAL   0x11ff0000

◆ NVIC_INIT_ITNS1

#define NVIC_INIT_ITNS1   1

◆ NVIC_INIT_ITNS1_VAL

#define NVIC_INIT_ITNS1_VAL   0x5dfb16fc

◆ NVIC_INIT_ITNS2

#define NVIC_INIT_ITNS2   1

◆ NVIC_INIT_ITNS2_VAL

#define NVIC_INIT_ITNS2_VAL   0x1f0fd99

◆ NVIC_INIT_ITNS3

#define NVIC_INIT_ITNS3   1

◆ NVIC_INIT_ITNS3_VAL

#define NVIC_INIT_ITNS3_VAL   0x24

◆ SAU_INIT_CTRL

#define SAU_INIT_CTRL   1

◆ SAU_INIT_CTRL_ALLNS

#define SAU_INIT_CTRL_ALLNS   0

◆ SAU_INIT_CTRL_ENABLE

#define SAU_INIT_CTRL_ENABLE   1

◆ SAU_INIT_END0

#define SAU_INIT_END0   0xffff /* end address of SAU region 0 */

◆ SAU_INIT_END1

#define SAU_INIT_END1   0x1007FFFF

◆ SAU_INIT_END2

#define SAU_INIT_END2   0x2000FFFF

◆ SAU_INIT_END3

#define SAU_INIT_END3   0xffff

◆ SAU_INIT_END4

#define SAU_INIT_END4   0x1007FFFF /* end address of SAU region 4 */

◆ SAU_INIT_END5

#define SAU_INIT_END5   0x00807FFF

◆ SAU_INIT_END6

#define SAU_INIT_END6   0x30017FFF

◆ SAU_INIT_END7

#define SAU_INIT_END7   0x5FFFFFFF

◆ SAU_INIT_NSC0

#define SAU_INIT_NSC0   1

◆ SAU_INIT_NSC1

#define SAU_INIT_NSC1   0

◆ SAU_INIT_NSC2

#define SAU_INIT_NSC2   1

◆ SAU_INIT_NSC3

#define SAU_INIT_NSC3   1

◆ SAU_INIT_NSC4

#define SAU_INIT_NSC4   0

◆ SAU_INIT_NSC5

#define SAU_INIT_NSC5   1

◆ SAU_INIT_NSC6

#define SAU_INIT_NSC6   0

◆ SAU_INIT_NSC7

#define SAU_INIT_NSC7   0

◆ SAU_INIT_REGION

#define SAU_INIT_REGION (   n)
Value:
SAU->RNR = (n & SAU_RNR_REGION_Msk); \
SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U

◆ SAU_INIT_REGION0

#define SAU_INIT_REGION0   1

◆ SAU_INIT_REGION1

#define SAU_INIT_REGION1   0

◆ SAU_INIT_REGION2

#define SAU_INIT_REGION2   0

◆ SAU_INIT_REGION3

#define SAU_INIT_REGION3   0

◆ SAU_INIT_REGION4

#define SAU_INIT_REGION4   1

◆ SAU_INIT_REGION5

#define SAU_INIT_REGION5   0

◆ SAU_INIT_REGION6

#define SAU_INIT_REGION6   1

◆ SAU_INIT_REGION7

#define SAU_INIT_REGION7   1

◆ SAU_INIT_START0

#define SAU_INIT_START0   0xf800 /* start address of SAU region 0 */

◆ SAU_INIT_START1

#define SAU_INIT_START1   0x10010000

◆ SAU_INIT_START2

#define SAU_INIT_START2   0x2000F000

◆ SAU_INIT_START3

#define SAU_INIT_START3   0xf800

◆ SAU_INIT_START4

#define SAU_INIT_START4   FMC_NON_SECURE_BASE /* start address of SAU region 4 */

◆ SAU_INIT_START5

#define SAU_INIT_START5   0x00807E00

◆ SAU_INIT_START6

#define SAU_INIT_START6   NON_SECURE_SRAM_BASE

◆ SAU_INIT_START7

#define SAU_INIT_START7   0x50000000

◆ SAU_REGIONS_MAX

#define SAU_REGIONS_MAX   8 /* Max. number of SAU regions */

◆ SCB_AIRCR_BFHFNMINS_VAL

#define SCB_AIRCR_BFHFNMINS_VAL   0

◆ SCB_AIRCR_PRIS_VAL

#define SCB_AIRCR_PRIS_VAL   0

◆ SCB_AIRCR_SYSRESETREQS_VAL

#define SCB_AIRCR_SYSRESETREQS_VAL   0

◆ SCB_CSR_AIRCR_INIT

#define SCB_CSR_AIRCR_INIT   1

◆ SCB_CSR_DEEPSLEEPS_VAL

#define SCB_CSR_DEEPSLEEPS_VAL   0

◆ SCU_INIT_IONSSET_VAL

#define SCU_INIT_IONSSET_VAL   0xff

◆ SCU_INIT_PNSSET0_VAL

#define SCU_INIT_PNSSET0_VAL   0x1012200

◆ SCU_INIT_PNSSET1_VAL

#define SCU_INIT_PNSSET1_VAL   0x60000

◆ SCU_INIT_PNSSET2_VAL

#define SCU_INIT_PNSSET2_VAL   0xf0221a8

◆ SCU_INIT_PNSSET3_VAL

#define SCU_INIT_PNSSET3_VAL   0x3f001f

◆ SCU_INIT_PNSSET4_VAL

#define SCU_INIT_PNSSET4_VAL   0x70007

◆ SCU_INIT_PNSSET5_VAL

#define SCU_INIT_PNSSET5_VAL   0x2330001

◆ SCU_INIT_PNSSET6_VAL

#define SCU_INIT_PNSSET6_VAL   0x30001

◆ SCU_SECURE_SRAM_SIZE

#define SCU_SECURE_SRAM_SIZE   0x4000